The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, when designing and manufacturing SRAM (static random access memory) cells having pull-up (PU) devices, pull-down (PD) devices, and pass-gate (PG) devices, it is common to form PU devices (e.g., PMOS) in one device region (e.g., in an n-well), and form PD and PG devices in another device region (e.g., in a p-well). However, at least for the PU devices, there is a concern that the spacing among them needs to be sufficiently large so that epitaxial source/drain (S/D) features of the PU devices do not merge to cause short defects. On the one hand, having large epitaxial S/D features are generally desirable for reducing S/D contact resistance. On the other hand, having large epitaxial S/D features also increases the spacing requirements among the PU devices, thereby undesirably reducing device integration. An object of the present disclosure seeks to resolve this issue, among others.